1. Field of the Invention
This invention relates to a defect compensation circuit for a solid-state imaging device in which an imaging output signal from a defective pixel is replaced by an imaging output signal from a defect-free pixel by way of performing a defect compensation.
In the present specification, the solid-state imaging device or CCD image sensor means an array of charge coupled devices (CCDs) in which electrical charges accumulated in one charge coupled device are transferred to the next for transferring data represented by electrical charges.
2. Description of Related Art
It is known that, in the solid-state imaging device, constituted by an array of semiconductor devices known as chargecoupled devices, deterioration in the picture quality is produced as a result of the imaging output from a defective pixel which outputs a signal of a peculiar level due to local crystal defects of the semiconductor in the absence of the incident light. The defective pixels in the solid-state imaging device may be typified by the black-flaw pixels and white-flaw pixels, the imaging outputs of which appear as black points and white points in the image displayed on a monitor screen, respectively.
Heretofore, in an imaging device making use of the CCD image sensor, as shown in FIG. 6, the CCD image sensor 21 is driven by a CCD driving circuit 24 operated responsive to timing signals generated by a timing signal generator 23 based on synchronizing signals generated by a synchronizing signal generator 22, so that the imaging signal charges of pixels are read line-sequentially at a time by means of a horizontal transfer register. An imaging output signal S.sub.OUT, sequentially read out from the pixels of the CCD image sensor 21, is outputted at an output terminal 26 by means of a sample-and-hold circuit 25.
The timing signal generator 23 is adapted for generating the above mentioned timing signals for operating the CCD driving circuit 24, while generating and outputting sampling pulses .phi..sub.SH adapted for operating the sample-and-hold circuit 25.
For avoiding deterioration in the picture quality due to the imaging output from defective pixels of the above described CCD image sensor by signal processing of the imaging output, defect data indicating the presence or absence of defects from pixel to pixel of the CCD image sensor 21 are stored in a memory and, as shown in FIG. 7, the operation of the timing signal generator 23, which applies a sampling pulse .phi..sub.SH to the sample-and-hold circuit 25, which in turn sample-holds the imaging output signal S.sub.OUT from the CCD image sensor 21, is controlled on the basis of the defect data read out from the memory 30 for withholding the sampling pulse .phi..sub.SH timed to the defective pixel of the CCD image sensor 21 by way of performing a defect compensation by a so-called 0'th order holding interpolation of substituting an imaging output from a normal pixel adjacent to the defective pixel for the imaging output from the defective pixel. This type of the defect compensation circuit is disclosed in, for example, the JP Patent Publication KOKOKU No. 61-43908 (1986).
With the defect compensation by the conventional 0'th order holding interpolation, if a boundary line l between the light and the dark of the object image is situated at a defective pixel P.sub.3, as shown by hatchings in FIG. 7, and the imaging output signal S.sub.OUT undergoes a transition in signal level, the sampling pulse .phi..sub.SH timed to the defective pixel P.sub.3 is withheld, as shown by a broken line, for substituting an imaging output S.sub.2, from the left-side adjacent normal pixel P.sub.2 for the imaging output S.sub.3 of the defective pixel P.sub.3, so that a correction error .DELTA. is produced.